1. Field
This invention relates generally to a charge pump, and more specifically, to a switching gate bias circuit in the charge pump.
2. Background
A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. The PLL is widely used in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, or distribute precisely timed clock pulses in digital logic circuits such as microprocessors.
The PLL may include a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The VCO generates an output signal. The phase detector receives an input signal compares the phase of the VCO-generated output signal with the phase of the input signal and adjusts the VCO to keep the phases matched. The output of the phase detector also acts as a current source to pump current into and out of the loop filter using the charge pump by turning the charge pump on and off periodically. However, when drain and source terminals of mirror transistors in the charge pump are switched, the voltage at the gate terminal (bias node) of the mirror transistors is also disturbed which degrades the transient behavior and linearity of the charge pump. When the charge-pump is nonlinear, noise of the delta sigma (ΔΣ) modulator (DSM) is folded in and the in-band noise is degraded in the PLL. One solution is to add an RC filter between the mirror transistors. However, this solution can significantly increase the area on a chip.